- 14 bit, 240MHz, pipelined ADC (Tested at 10MHz)
- LVDS output with 3.3V CMOS trim
- High-dynamic range
- Made up of the following six blocks
- Analog input stage: 4Vp-p differential input range (2Vp-p, +1 to –1, per
- The output state: 14 differential LVDS (±200mV around 1.2V) outputs, 1 differential over-range
bit and a differential Data Valid output signal.
- Analog Clock input: 20Khz to 10MHz differential clock at 10dbm driving a 25-ohm load.
- Trim control and read back
- Reference Voltage distribution Block
- A Scan In digitizer test mode block used to bypass the Analog input to test the output stage of the
- Used in communication base stations.